89#define portFLOAT float
90#define portDOUBLE double
92#define portSHORT short
93#define portSTACK_TYPE uint32_t
94#define portBASE_TYPE long
96typedef portSTACK_TYPE task_stack_t;
98typedef unsigned long uint32_t;
100typedef uint32_t uint32_t;
101#define portMAX_DELAY ( uint32_t ) 0xffffffffUL
105#define portTICK_TYPE_IS_ATOMIC 1
110#define portSTACK_GROWTH ( -1 )
111#define portTICK_PERIOD_MS ( ( uint32_t ) 1000 / configTICK_RATE_HZ )
112#define portBYTE_ALIGNMENT 8
119#define portEND_SWITCHING_ISR( xSwitchRequired )\
121extern uint32_t ulPortYieldRequired; \
123 if( xSwitchRequired != pdFALSE ) \
125 ulPortYieldRequired = pdTRUE; \
129#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
130#define portYIELD() __asm volatile ( "SWI 0" );
137extern void vPortEnterCritical(
void );
138extern void vPortExitCritical(
void );
139extern uint32_t ulPortSetInterruptMask(
void );
140extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
141extern void vPortInstallFreeRTOSVectorTable(
void );
145#define portENTER_CRITICAL() vPortEnterCritical();
146#define portEXIT_CRITICAL() vPortExitCritical();
147#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
148#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
149#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
150#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
157#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
158#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
162void FreeRTOS_Tick_Handler(
void );
169#if( configUSE_TASK_FPU_SUPPORT != 2 )
170 void vPortTaskUsesFPU(
void );
174 #define vPortTaskUsesFPU()
176#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
178#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
179#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
182#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
183 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
186#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
189 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
190 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
194 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
199 void vPortValidateInterruptPriority(
void );
200 #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
203#define portNOP() __asm volatile( "NOP" )
204#define portINLINE __inline
213#if configUNIQUE_INTERRUPT_PRIORITIES == 16
214 #define portPRIORITY_SHIFT 4
215 #define portMAX_BINARY_POINT_VALUE 3
216#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
217 #define portPRIORITY_SHIFT 3
218 #define portMAX_BINARY_POINT_VALUE 2
219#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
220 #define portPRIORITY_SHIFT 2
221 #define portMAX_BINARY_POINT_VALUE 1
222#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
223 #define portPRIORITY_SHIFT 1
224 #define portMAX_BINARY_POINT_VALUE 0
225#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
226 #define portPRIORITY_SHIFT 0
227 #define portMAX_BINARY_POINT_VALUE 0
229 #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
233#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
234#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
235#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
236#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
237#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
239#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
240#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
241#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
242#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
243#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
244#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
245#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )